1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that performs burst order control (BOC) and data bus inversion (DBI). The present invention also relates to a data processing system including such a semiconductor device.
2. Description of Related Art
DDR3, the dominant standard of dynamic random access memory (DRAM), and the next-generation standard DDR4 use a technology called BOC for suitable random access. For example, by BOC with a burst length of eight, the output order of eight bits of read data to be consecutively output from a data input/output terminal is rearranged according to three bits of column address Y0, Y1, and Y2 that are input from an external controller. The external controller can thus take out the pieces of data stored in memory cells in a desired order. BOC is not applied to write data. Japanese Patent Application Laid-Open No. H06-290582 discloses an example of BOC.
DDR4 is expected to include an additional technology called DBI. According to the DBI technology, eight bits (DQ0 to DQ7) of read data to be simultaneously output are all inverted if five or more of the eight bits are “0”. Since “1” consumes less power than “0” for transmission, DBI can be employed to reduce power consumption. By DBI, one bit of DBI data indicating whether eight bits of read data are inverted is output with the eight bits of read data. The DBI data is output through a dedicated terminal (DBI terminal) which is provided separate from data input/output terminals for outputting the read data. DBI is also applied to write data. At the time of writing, the DRAM performs internal processing for restoring inverted bits based on DBI data input from the controller. U.S. Pat. No. 7,405,981 discloses a general example of DBI different from that of the DDR4 specifications.
A DDR4 DRAM includes a BOC circuit and a DBI circuit for implementing the foregoing BOC and DBI, respectively. At the time of reading, 64 bits of read data read from the memory array are initially supplied to the DBI circuit through a read/write bus RWBUS_ARAY which includes 64 bus lines. The DBI circuit inverts the supplied 64 bits of read data when needed, and outputs the resultant to the BOC circuit with additional eight bits of DBI data. The BOC circuit rearranges the output order of a total of 72 bits of data, including the 64 bits of read data and the eight bits of DBI data, according to the column address Y0, Y1, and Y2. The BOC circuit outputs the resultant to a data input/output circuit through a read/write bus RWBUS_DQ and a read/write bus RWBUS_DBI.
According to such a configuration, the BOC circuit needs to be provided for each of nine output terminals, including eight data input/output terminals and the DBI terminal. In other words, nine BOC circuits are needed. Since the BOC circuits include a large number of transfer gates, the provision of as many as nine BOC circuits (the ninth BOC circuit) increases the circuit area. Also, the higher power consumption also needs a reduction of the BOC circuits.